1. Field of the Invention
This invention relates to a random access memory device and, more particularly, to a method of fabricating a three-dimensional stacked capacitors having increased capacitance.
2. Description of the Prior Art
The integrated circuit density on the semiconductor substrate and the semiconductor chips formed therefrom, has dramatically increased in recent years. This increase in density has resulted from down scaling of the individual devices built in and on the substrate and the increase in packing density. Future requirements for even greater increases in packing density, such as in ultra large semiconductor integration (ULSI), is putting additional demand on the semiconductor technologies and more particularly on the photolithographic techniques.
One circuit type experiencing this demand for increased density is the array of charge storage cells on a dynamic random access memory (DRAM) chip. These individual DRAM storage cells, consisting usually of a single metal-oxide-semiconductor field-effect transistor (MOSFET) and a single capacitor are used extensively in the electronics industry for storing data. A single DRAM storage cell stores a bit of data on the capacitor as electrical charge.
As the array of cells increase on the DRAM chip and capacitor decrease in size, it becomes increasingly more difficult to maintain sufficient charge on the storage capacitor to maintain an acceptable signal-to-noise level. These volatile storage cells also require more frequent refresh cycles in order to retain their charge.
since the storage capacitor must occupy an area limited by the cell size, in order to accommodate the array capacitors on the chip, it is necessary to explore alternative methods for increasing the capacitance without increasing the area that the capacitor occupies on the substrate surface.
Both a trench capacitor, formed in the substrate, and a stacked capacitor, formed on the surface and over the MOSFET, are being pursued for DRAM applications. The stacked capacitors has received considerable interest in recent years because of the variety of ways that its shape can be controlled to increase the capacitance without increasing the area it occupies on the substrate. This makes the stacked capacitor very desirable for DRAM application.
Numerous three-dimensional capacitor structures have been reported. For example, H-H. Tseng, U.S. Pat. No. 5,192,702 teaches methods of fabricating vertical sidewall capacitors and P. Fazan et al, U.S. Pat. No. 5,084,405 teaches methods of forming double ring stacked capacitors structures using sidewall spacer techniques.
However, one special type of three-dimensional stacked capacitor structure receiving considerable interest is the capacitor having a fin shaped electrode extending up-ward and over the cell area. The potential of stacking increased number of fin structures on the electrode and thereby further increasing the capacitance is of much interest. For example, an early publication by T. Ema et al entitled"3 -Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS" , International Electron Devices Meeting, 1988 , pp 593-595 , IEEE, report on the use of multi-layers of polysilicon and insulators to form this capacitor structure. More recently, variation of this fin stacked capacitor structure have been proposed to improve earlier versions. See for example, P. Fazan et al U.S. Pat. No. 5,053,351, M. Taguchi U.S. Pat. No. 5,021,357 and C. Kudoh et al, U.S. Pat. No. 5,223,729. Most of these stacked fin capacitor structures require multiple deposition of conducting layers and insulating layers and additional etch steps. This additional processing in more than one processing system result in additional manufacturing cost and reduced reliability and yield.
Another approach by Y. Kohyana et al U.S. Pat. No. 5,142,639 teaches a method of using alternate layers of dissimilar insulating layers and then etches an opening in this multi-layer to the contact and selectively etching one of the insulating layers to form a fin-like template for forming thereon the bottom and top electrodes of the stacked capacitor.
Although there has been considerable work done to increase the capacitance area on these very small fin shaped stacked capacitors, it is still desirable to further improve these capacitors while retaining as simple a manufacturing process as possible. In many of these fin structured stacked capacitors a multilayer is formed and then the multilayer is etched open to the source/drain contact to form the node contact for the stacked capacitor. These contact openings are usually formed using anisotropic etching in a plasma etcher that require a D.C. (Direct Current) electrical bias on the substrate electrode upon which the substrates are placed within the etcher. The D.C. bias is required to achieve the directional etching of the sidewalls in the contact opening, but can also result in device degradation at the substrate surface. Therefore, it is highly desirable to have device processing that avoid this exposure to plasma etching, whenever possible.